MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 292

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Reset
7.3
The MPC561/MPC563 supports data coherency and avoids data corruption during reset. If a cycle is
executing when any SRESET or HRESET source is detected, then the cycle will either complete or will
not start before generating the corresponding reset control signal. There are reset sources, however, when
the MPC561/MPC563 generates an internal reset due to special internal situations where this protection is
not supported. See
In the case of large operand size (32 or 16 bits) transactions to a smaller port size, the cycle is split into
two 16-bit or four 8-bit cycles. In this case, data coherency is assured and data will not be corrupted.
In the case where the core executes an unaligned load/store cycle which is broken down into multiple
cycles, data coherency is NOT assured between these cycles (i.e., data could be corrupted).
Contention may occur if a write access is in progress to external memory and SRESET/HRESET is
asserted and the external reset configuration word (RCW) is used. In this case, the external RCW drivers,
usually activated by HRESET/SRESET lines, will drive the data bus together with the MPC561/MPC563.
Thus the data in the RAM may be corrupted regardless of the data coherency mechanism in the
MPC561/MPC563.
7-4
HRESET
Power-On Reset
(PORESET)
Hard Reset (HRESET)
Sources:
Soft Reset (SRESET)
Sources:
• External Hard Reset
• Loss of Lock
• On-Chip Clock Switch
• Illegal Low-Power Mode
• Software Watchdog
• Checkstop
• Debug Port Hard Reset
• External Soft Reset
• Debug Port Soft Reset
• JTAG Reset
Data Coherency During Reset
Reset Source
Reset Driven
Table 7-2. Reset Configuration Word and Data Corruption/Coherency
Section 7.4, “Reset Status Register
Table 7-1. Reset Action Taken for Each Reset Cause
Logic and
States
Reset
Reset
PLL
MPC561/MPC563 Reference Manual, Rev. 1.2
Yes
No
No
SRESET
Coherency (EXT_RESET)
Reset to Use for Data
Configuratio
n Reset
System
Yes
Yes
No
Module
Clock
Reset
(RSR).”
Yes
Yes
No
HRESET
Driven
Yes
Yes
Pin
No
Configuratio
Debug Port
Yes
Yes
Yes
n
Comments
Freescale Semiconductor
Internal
Reset
Other
Logic
Yes
Yes
Yes
SRESET
Driven
Pin
Yes
Yes
Yes