MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 675

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

The operation of the receiver bit processor is shown in
search for a valid start bit and the synchronization procedure as outlined above. The possibilities of noise
durations greater than one bit-time are not considered in this examples.
15.7.7.8
The RE bit in SCCxR1 enables (RE = 1) and disables (RE = 0) the receiver. The receiver contains a receive
serial shifter and a parallel receive data register (RDRx) located in the SCI data register (SCxDR). The
serial shifter cannot be directly accessed by the CPU. The receiver is double-buffered, allowing data to be
held in the RDRx while other data is shifted in.
Receiver bit processor logic drives a state machine that determines the logic level for each bit-time. This
state machine controls when the bit processor logic is to sample the RXD pin and also controls when data
is to be passed to the receive serial shifter. A receive time clock is used to control sampling and
synchronization. Data is shifted into the receive serial shifter according to the most recent synchronization
of the receive time clock with the incoming data stream. From this point on, data movement is
synchronized with the MCU IMB3 clock. Operation of the receiver state machine is detailed in the Queued
Serial Module Reference Manual.
The number of bits shifted in by the receiver depends on the serial format. However, all frames must end
with at least one stop bit. When the stop bit is received, the frame is considered to be complete, and the
received data in the serial shifter is transferred to the RDRx. The receiver data register flag (RDRF) is set
when the data is transferred.
The stop bit is always a logic one. If a logic zero is sensed during this bit-time, the FE flag in SCxSR is
set. A framing error is usually caused by mismatched baud rates between the receiver and transmitter or
by a significant burst of noise. Note that a framing error is not always detected; the data in the expected
stop bit-time may happen to be a logic one.
Noise errors, parity errors, and framing errors can be detected while a data stream is being received.
Although error conditions are detected as bits are received, the noise flag (NF), the parity flag (PF), and
the framing error (FE) flag in SCxSR are not set until data is transferred from the serial shifter to the RDRx.
Freescale Semiconductor
1
R
T
1
*
* Restart RT Clock
1 1 1
R
T
1
* *
Receiver Functional Operation
R
T
1
R
T
1
* *
R
T
1
1
1
R
T
1
* *
1
R
T
1
1 1
R
T
1
* *
R
T
1
MPC561/MPC563 Reference Manual, Rev. 1.2
R
T
1
0
Figure 15-30. Start Search Example
R
T
2
0
R
T
3
R
T
4
Perceived Start Bit
0
R
T
5
Actual Start Bit
R
T
6
0 0
R
T
7
R
T
8
Figure
R
T
9
0 0
R
T
1
0
R
T
1
1 2
15-30. This example demonstrates the
R
T
1
R
T
1
3 4
R
T
1
R
T
1
5 6
R
T
1
*
Queued Serial Multi-Channel Module
R
T
1
R
T
2
R
T
3
LSB
15-57