MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 88

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Overview
1.3.1.1
1.3.1.2
1.3.1.3
1-4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PowerPC
Precise exception model
64-bit floating point unit (FPU)
Code compression supported on MPC562/MPC564
Reduces usage of internal/external Flash memory (up to 50% for code) on the MPC564
Reduces code size up to 50%
Extensive system development support
On-chip watchpoints and breakpoints
Program flow tracking capability
System configuration and protection features:
— Periodic-interrupt timer
— Bus monitor
— Software watchdog timer
— Real-time clock (RTC)
— PPC decrementer
— Time base
Clock synthesizer
Power management
Reset controller
External bus interface that tolerates 5-V inputs, provides 2.6-V outputs, and supports multi-master
designs
Enhanced interrupt controller that supports up to eight external and 40 internal interrupts,
simplifies the interrupt structure, and decreases interrupt processing time
USIU supports dual mapping to map part of one internal/external memory to another external
memory
External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions per
memory cycle
Support for enhanced interrupt controller (EIC)
Support for enhanced exception table relocation feature
Branch target buffer
Contains 2 Kbytes of decompression RAM (DECRAM) for code compression. This RAM may
also be used as general-purpose RAM when the code compression feature is not used.
RISC MCU Central Processing Unit (RCPU)
Unified System Interface Unit (USIU)
Burst Buffer Controller (BBC) Module
ΤΜ
-compliant 32-bit single issue core
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor