MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1263
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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F.12
Note: (V
Freescale Semiconductor
DD
1
2
49a
55a
43
44
45
46
47
48
49
50
51
52
53
54
55
Weak pull-ups and pull-downs used for Reset timing will comply with the 130 µA mode select current
outlined in <XrefBlue>Table F.5 on page F-7 The system requires two clocks of hold time on
RSTCONF/TEXP after negation of HRESET. The simplest way to insure meeting this requirement in
systems that require the use of the TEXP function, is to connect RSTCONF/TEXP to SRESET.
HRESET, SRESET and PORESET have a glitch detector to ensure that spikes less than 20 ns are rejected.
The internal HRESET, SRESET and PORESET will assert only if these signals are
asserted for more than 100 ns
RESET Timing
= 2.6 V ± 0.1 V, V
CLKOUT to HRESET high
impedance
CLKOUT to SRESET high
impedance
RSTCONF pulse width
Configuration Data to HRESET
rising edge Setup Time
Configuration Data to RSTCONF
rising edge set up time
Configuration Data hold time after
RSTCONF negation
Configuration Data hold time after
HRESET negation
RSTCONF hold time after HRESET
negation
HRESET and RSTCONF asserted to
Data out drive
RSTCONF negated to Data out high
impedance
CLKOUT of last rising edge before
chip tristates HRESET to Data out
high impedance
DSDI, DSCK set up
DSDI, DSCK hold time
SRESET negated to CLKOUT
rising edge for DSDI and DSCK
sample
HRESET, SRESET, PORESET
pulse width
1
Characteristic
2
DDH
= 5.0 V ± 0.25 V, T
MPC561/MPC563 Reference Manual, Rev. 1.2
Table F-14. RESET Timing
A
= T
15 * TC + TCC
15 * TC + TCC
L
Expression
to T
17 * TC
3 * TC
8 * TC
H
)
Min
425
382
382
200
100
50
25
25
25
75
0
0
0
40 MHz
Max
20
20
Min
302
272
272
142
100
35
25
25
25
55
0
0
0
56 MHz
Max
Electrical Characteristics
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
F-47
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