MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 511

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
If the gate closes before queue 1 completes execution, the current CCW completes execution of queue 1
stops and QADC64E sets the PF1 bit to indicate an incomplete queue. Software can read the CWPQ1 to
determine the last valid conversion in the queue. In this mode, if the gate opens again, execution of queue
1 begins again. The start of queue 1 is always the first CCW in the CCW table.
Since the condition of the gate is only sampled after each conversion during queue execution, closing the
gate for a period less than a conversion time interval does not guarantee the closure will be captured.
13.5.4.4.4
Periodic/Interval Timer Continuous-Scan Mode
The QADC64E includes a dedicated periodic/interval timer for initiating a scan sequence on queue 1
and/or queue 2. Software selects a programmable timer interval ranging from 128 to 128 Kbytes times the
QCLK period in binary multiples. The QCLK period is prescaled down from the IMB3 MCU clock.
When a periodic/interval timer continuous-scan mode is selected for queue 1 and/or queue 2, the timer
begins counting. After the programmed interval elapses, the timer generated trigger event starts the
appropriate queue. Meanwhile, the QADC64E automatically performs the conversions in the queue until
an end-of-queue condition or a pause is encountered. When a pause occurs, the QADC64E waits for the
periodic interval to expire again, then continues with the queue. Once end-of-queue has been detected, the
next trigger event causes queue execution to begin again with the first CCW in the queue.
The periodic/interval timer generates a trigger event whenever the time interval elapses. The trigger event
may cause the queue execution to continue following a pause or queue completion, or may be considered
a trigger overrun. As with all continuous-scan queue operating modes, software action is not needed
between trigger events. Since both queues may be triggered by the periodic/interval timer, see
Section 13.5.6, “Periodic / Interval
Timer” for a summary of periodic/interval timer reset conditions.
Software enables the completion interrupt when using the periodic/interval timer continuous-scan mode.
When the interrupt occurs, the software knows that the periodically collected analog results have just been
taken. The software can use the periodic interrupt to obtain non-analog inputs as well, such as contact
closures, as part of a periodic look at all inputs.
13.5.5
QADC64E Clock (QCLK) Generation
Figure 13-24
is a block diagram of the clock subsystem. The QCLK provides the timing for the A/D
converter state machine which controls the timing of the conversion. The QCLK is also the input to a
17-stage binary divider which implements the periodic/interval timer. To retain the specified analog
conversion accuracy, the QCLK frequency (F
) must be within the tolerance specified in
Appendix F,
QCLK
“Electrical
Characteristics.”
Before using the QADC64E, the software must initialize the prescaler with values that put the QCLK
within the specified range. Though most software applications initialize the prescaler once and do not
change it, write operations to the prescaler fields are permitted.
For software compatibility with earlier versions of QADC64E, the definition of PSL, PSH, and PSA have
been maintained. However, the requirements on minimum time and minimum low time no longer exist.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-47