MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 747

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

17.6.1.4
The MIOS14MCR register is a collection of read/write stop, freeze, reset, and supervisor bits, as well as
interrupt arbitration number bits. These bits are detailed in
Freescale Semiconductor
SRESET
Bits
Bits
8:15
4:7
0:7
0
1
2
3
Field STOP RSV
Addr
MIOS14 Module Configuration Register (MIOS14MCR)
Name
STOP
Name
MSB
RST
FRZ
MN
VN
0
—
—
1
Module number = 0x0E on the MPC561/MPC563
Version number. May change with different revisions of the device.
Stop enable — The STOP bit, while asserted, activates the MIOB freeze signal regardless of the
state of the IMB3 FREEZE signal. The MIOB freeze signal is further validated in some
submodules with internal freeze enable bits in order for the submodule to be stopped. The
MBISM continues to operate to allow the CPU access to the submodule’s registers. The MIOB
freeze signal remains active until reset or until the STOP bit is written to zero by the CPU (via the
IMB3). The STOP bit is cleared by reset.
0 Allows MIOS14 operation.
1 Selectively stops MIOS14 operation.
Reserved
Freeze enable — The FRZ bit, while asserted, activates the MIOB freeze signal only when the
IMB3 FREEZE signal is active. The MIOB freeze signal is further validated in some submodules
with internal freeze enable bits in order for the submodule to be frozen. The MBISM continues to
operate to allow the CPU access to the submodule’s registers. The MIOB freeze signal remains
active until the FRZ bit is written to zero or the IMB3 FREEZE signal is negated. The FRZ bit is
cleared by reset.
0 Ignores the FREEZE signal on the IMB3, allows MIOS14 operation.
1 Selectively stops MIOS14 operation when the FREEZE signal appears on the IMB3.
Module reset — The RST bit is always read as 0 and can be written to 1. When the RST bit is
written to 1 operation of the MIOS14 completely stops and resets all the values in the submodule.
This completely stops the operation of the MIOS14 and reset all the values in the submodules
registers that are affected by reset. This bit provides a way of resetting the complete MIOS14
module regardless of the reset state of the CPU. The RST bit is cleared by reset.
0 Writing a 0 to RST has no effect.
1 Reset the MIOS14 submodules.
Reserved
Figure 17-7. Module Configuration Register (MIOS14MCR)
FRZ
2
RST
Table 17-5. MIOS14MCR Bit Descriptions
Table 17-4. MIOS14VNR Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
3
4
5
—
0000_0000_0000_0000
6
0x30 6806
7
Description
Description
Table
SUPV
8
17-5.
9
Modular Input/Output Subsystem (MIOS14)
10
11
—
12
13
14
LSB
15
17-15