MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1108

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

MPC562/MPC564 Compression Features
A-20
15:21
24:31
Bits
8:14
0:3
4:7
22
23
TP1LEN
TP2LEN
TP1BA
TP2BA
Name
AS
DS
—
Length and Type of Table Pointer 1. This field’s value defines the length of the field that contains
a pointer to the first vocabulary table allocated for the class.
0x0 Empty field
0x1 Reserved
0x2 TP1 length is 2 bits
0x3 TP1 length is 3 bits
0x4 TP1 length is 4 bits
0x5 TP1 length is 5 bits
0x6 TP1 length is 6 bits
0x7 TP1 length is 7 bits
0x8 TP1 length is 8 bits
0x9 TP1 length is 9 bits
0xA to 0xFReserved
Length and Type of Table Pointer 2. This field’s value defines the length of the field that contains
either a pointer to the second vocabulary table allocated for the class or a bypass field.
0x0 Empty field
0x1 Reserved
0x2 TP2 length is 2 bits
0x3 TP2 length is 3 bits
0x4 TP2 length is 4 bits
0x5 TP2 length is 5 bits
0x6 TP2 length is 6 bits
0x7 TP2 length is 7 bits
0x8 TP2 length is 8 bits
0x9 TP2 length is 9 bits
0xA Reserved
0xB TP2 field is a 0 bit compact bypass field
0xC TP2 field is a 10 bits compact bypass field
0xD TP2 field is a 15 bits compact bypass field
0xE TP2 field is a 16 bits bypass field
0xF Reserved.
Base address for vocabulary table in RAM Bank 1. This field specifies the base page address
of the class’ vocabulary table that resides in RAM Bank 1.
Base address for vocabulary table in RAM Bank 2. This field specifies the base page address
of the class’ vocabulary table that resides in RAM Bank 2.
Address Swap specification
0 Address swap operation will not be performed for the class.
1 Address swap operation will be performed for the class
For further details concerning AS operation refer to
Data swap specification
0 Data swap operation will not be performed for the class.
1 Data swap operation will be performed for the class.
For further details concerning DS operation refer to
Reserved
Table A-3. DCCR0-DCCR15 Field Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Table
Table
A-4.
A-4.
Freescale Semiconductor