MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 803

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

samples and subtract them to get the pulse width. The leading edge sample is double latched so that the
software has the time of one full period of the input signal to read the samples to be sure that nothing is
lost. Depending on the prescaler divide ratio, pulse width from 50 ns to 6.7 s can be measured. Note that
a software option is provided to also generate an interrupt after the first edge.
In the example shown in
configured in the input pulse width measurement mode. When the leading edge (programmed for being
either rising or falling) of the input signal occurs, the state of the 16-bit counter bus is saved in register B1.
When the trailing edge occurs, the 16-bit counter bus is latched into register A and the content of register
B1 is transferred to register B2. This operation leaves register B1 free for the next leading edge to occur
on the next clock cycle. When enabled, an interrupt is provided after the trailing edge, to notify the
software that pulse width measurement data is available for a new pulse. After the trailing edge, the
software has one cycle time of the input signal to obtain the values for each edge. When software attention
is not needed for every pulse, the interrupt can be disabled. The software can read registers A and B2
coherently (using a 32-bit read instruction) at any time, to get the latest edge measurements. The software
work is less than half that needed with a timer that requires the software to read one edge and save the
value and then wait for the second edge.
17.13.2 MIOS14 Input Double Edge Period Measurement
Two samples are available to the software from an MIOS14 double action submodule for period
measurement. The software can read the previous and the current edge samples and subtract them. As with
pulse width measurement, the software can be sure not to miss samples by ensuring that the interrupt
response time is faster than the fastest input period. Alternately, when the software is just interested in the
latest period measurement, one 32-bit coherent read instruction can get both the current and the previous
samples. Depending on the prescaler divide ratio, period times can be measured from 50 ns to 6.7 s.
Freescale Semiconductor
MIOS14 Modulus Counter Submodule
Prescaler
Select
Clock
or Pin
From
Figure 17-43. MIOS14 Example: Double Capture Pulse Width Measurement
16-bit Up-Counter
Figure
17-43, a counter submodule is used as the time-base for a MDASM
MPC561/MPC563 Reference Manual, Rev. 1.2
Submodule Bus
Counter
Buses
16-bit
Two
Select
in IPWM mode (MOD3-MOD0 = 0b0001)
Bus
MIOS14 Double Action Submodule
16-bit Register A
16-bit Register B1
16-bit Register B2
Modular Input/Output Subsystem (MIOS14)
Interrupt
Capture
Trailing
Detect
Edge
Input
Edge
on
Signal
Input
17-71