MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 946

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Development Support
Note: DSCK and DSDI transitions are not required to be synchronous with CLKOUT.
23-32
DSDO
DSCK
DSDI
CLKOUT
DSDO
DSDI
Debug Port drives “ready” bit onto DSDO when ready for a new transmission.
Debug Port drives “ready” bit onto DSDO when CPU starts a read of DPIR or DPDR.
Figure 23-10. Synchronous Self Clock Serial Communication
READY
Figure 23-9. Asynchronous Clock Serial Communications
READY
START
Development Tool drives the “start” bit on DSDI (after detecting “ready” bit on
DSDO when in debug mode). The “start” bit is immediately followed by
a mode bit and a control bit and then 7 or 32 input data bits.
Development Tool drives the “start” bit on DSDI (after detecting “ready” bit on
DSDO when in debug mode). The “start” bit is immediately followed by
a mode bit and a control bit and then 7 or 32 input data bits.
START
MPC561/MPC563 Reference Manual, Rev. 1.2
MODE
S<0> S<1>
S<0>
MODECNTRLDI<0>
Debug Port detects the “start” bit on DSDI and follows
the “ready” bit with two status bits and 7 or 32 output data bits.
CNTRL
Debug Port detects the “start” bit on DSDI and follows
the “ready” bit with two status bits and 7 or 32 output data bits.
S<1>
DO
<0 >
DO<0>
DI<0>
DI<1>
DO
<1 >
DI<
<N-3>
<N-3>
1
DO
<N-2>
<N-2>
DI
DO
DI
<N-2>
<N-2>
DO
DI
<N-1>
<N-1>
DO
<N-1>
DI
<N-1>
DO
DI
<N>
DO
<N>
<N>
<N>
DO
DI
DI
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