MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 313

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

The general system clock frequency can be switched between different values. The highest operational
frequency can be achieved when the system clock frequency is determined by DFNH (CSRC bit in the
PLPRCR is cleared) and DFNH = 0 (division by one). The general system clock can be operated at a low
frequency (gear mode) or a high frequency. The DFNL bits in SCCR define the low frequency. The DFNH
bits in SCCR define the high frequency.
The frequency of the general system clock can be changed dynamically with the system clock control
register (SCCR), as shown in
The frequency of the general system clock can be changed “on the fly” by software. The user may simply
cause the general system clock to switch to its low frequency. However, in some applications, there is a
need for a high frequency during certain periods. Interrupt routines, for example, may require more
performance than the low frequency operation provides, but must consume less power than in maximum
frequency operation. The MPC561/MPC563 provides a method to automatically switch between low and
high frequency operation whenever one of the following conditions exists:
When neither of these conditions exists and the CSRC bit in PLPRCR is set, the general system clock
switches automatically back to the low frequency.
Abrupt changes in the divide ratio can cause linear changes in the operating currents of the
MPC561/MPC563.
When the multiplication factor (PLPRCR[MF]) for the PLL is changed, the PLL stops all internal clocks
until the PLL adjusts to the new frequency. This includes stopping the clock to the watchdog timer,
therefore SWT cannot reset the system during this period.
When the clock stops, the current consumed by the device from VDD will fall; it will then rise sharply
when the PLL turns on the PLL output clocks at the new frequency. These abrupt changes in the divide
ratio can cause linear changes in the operating currents of the device. Insure that the proper power supply
filtering is available to handle changes instantaneously. The gear modes (DFNH and DFNL) can be used
to temporarily decrease the system frequency to minimize the demand on the power supply when the MF
or DIVF multiply/divide ratio is changed.
When the general system clock is divided, its duty cycle is changed. One phase remains the same (for
example, 12.5 ns at 40 MHz) while the other becomes longer.
Freescale Semiconductor
•
•
VCO/2 (e.g., 40 MHz)
There is a pending interrupt from the interrupt controller. This option is maskable by the PRQEN
bit in the SCCR.
The (POW) bit in the MSR is clear in normal operation. This option is maskable by the PRQEN
bit in the SCCR.
O
Figure
DFNH Divider
DFNL Divider
Figure 8-5. General System Clocks Select
MPC561/MPC563 Reference Manual, Rev. 1.2
8-5.
DFNH
DFNL
O
O
Normal
Low Power
O
General System Clock
Clocks and Power Control
8-11