MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 34

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

24.14
24.14.1
24.14.1.1
24.14.1.2
24.14.1.3
24.14.1.4
24.14.2
24.14.2.1
24.14.2.2
24.14.2.3
24.14.2.4
24.14.3
24.14.4
24.15
24.15.1
24.15.2
25.1
25.1.1
25.1.2
25.1.2.1
25.1.2.2
25.1.3
25.1.3.1
25.1.3.2
25.1.3.3
25.1.3.4
25.1.4
25.2
25.2.1
25.2.2
A.1
A.2
xxxiv
Paragraph
Number
IEEE 1149.1 Test Access Port ...................................................................................... 25-1
MPC561/MPC563 Restrictions .................................................................................. 25-32
ICDU Key Features ........................................................................................................ A-1
Class-Based Compression Model Main Principles......................................................... A-1
RCPU Development Access ...................................................................................... 24-76
Power Management ................................................................................................... 24-86
RCPU Development Access Messaging ................................................................. 24-77
RCPU Development Access Operation .................................................................. 24-79
Throughput .............................................................................................................. 24-82
Development Access Timing Diagrams ................................................................. 24-82
Functional Description ............................................................................................ 24-86
Low Power Modes .................................................................................................. 24-86
Overview ................................................................................................................... 25-2
Entering JTAG Mode ................................................................................................ 25-3
Instruction Register ................................................................................................. 25-30
HI-Z ........................................................................................................................ 25-32
Non-Scan Chain Operation ..................................................................................... 25-32
BSDL Description ................................................................................................... 25-33
DSDI Message .................................................................................................... 24-77
DSDO Message .................................................................................................. 24-78
BDM Status Message ......................................................................................... 24-78
Error Message (Invalid Message) ....................................................................... 24-79
Enabling RCPU Development Access Via READI Signals ............................... 24-80
Entering Background Debug Mode (BDM) Via READI Signals ...................... 24-80
Non-Debug Mode Access of RCPU Development Access ................................ 24-80
RCPU Development Access Flow Diagram ....................................................... 24-81
TAP Controller ..................................................................................................... 25-4
Boundary Scan Register ....................................................................................... 25-4
EXTEST ............................................................................................................. 25-31
SAMPLE/PRELOAD ......................................................................................... 25-31
BYPASS ............................................................................................................. 25-31
CLAMP ............................................................................................................... 25-32
MPC562/MPC564 Compression Features
IEEE 1149.1-Compliant Interface (JTAG)
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Appendix A
Chapter 25
Title
Freescale Semiconductor
Number
Page