MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 203

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

See
When a data protection error exception is taken, instruction execution resumes at offset 0x1400 from the
base address indicated by MSR[IP].
3.15.4.16 Implementation-Dependent Debug Exceptions
Implementation-dependent debug exceptions occur in the following cases:
See
Freescale Semiconductor
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Table 3-36
Table 3-37
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during a data access in Decompression On mode, the SRR0 register will contain the address
of the Load/Store instruction in compressed format.
Machine State Register (MSR)
Data Address Register (DAR)
Data/Storage Interrupt Status
When there is an internal breakpoint match (for more details, refer to
Support.”
When a peripheral breakpoint request is asserted to the RCPU.
When the development port request is asserted to the RCPU. Refer to
Support,” for details on how to generate the development port-interrupt request.
Register (DSISR)
Register Name
for data-protection-error exception register settings.
for debug-exception register settings.
Table 3-36. Register Settings Following a Data Protection Error Exception
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
Other
Other
Bits
0:15
7:31
ME
0:3
LE
All
All
IP
4
5
6
Set to the effective address of the instruction that caused the
exception
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
Set to 1 if the storage access is not permitted by the protection
mechanism. Otherwise cleared to 0
Cleared to 0
Set to 1 for a store operation and cleared to 0 for a load
operation
Cleared to 0
exception
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
No change
Cleared to 0
Set to the effective address of the data access that caused the
Description
Chapter 23, “Development
Chapter 23, “Development
Central Processing Unit
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