MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 225

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

4.6.2
4.6.2.1
Freescale Semiconductor
1
2
,
HRESET
HRESET
MPC562/MPC564 only.
The reset value is a reset configuration word value extracted from the internal bus line. Refer to
Configuration Word
Bits
8:17
Field R
Field
Addr
3:7
18
0
1
2
MSB
16
BBC Register Descriptions
0
—
BBC Module Configuration Register (BBCMCR)
000
17
D
1
Name
TEST
BE ETRE EIR
BE
18
S
—
2
R
D
S
(RCW).”
1
ID19
Figure 4-7. BBC Module Configuration Register (BBCMCR)
19
3
2
Read Only. Any attempt to write to the DECRAM array while R is set is terminated with
an error. This causes a machine check exception for RCPU.
0 DECRAM array is Readable and Writable.
1 DECRAM array is Read only.
Data Only. The DECRAM array may be used for Instructions and Data or for Data
storage only. Any attempt to load instructions from the DECRAM array, while D is set, is
terminated with an error This causes a machine check exception for the RCPU.
0 DECRAM array holds Data and/or Instruction.
1 DECRAM array holds Data only.
Supervisor Only.
When the bit is set (S = 1), only a Supervisor program may access the DECRAM. If a
Supervisor program is accessing the array, normal read/write operation will occur. If a
User program is attempting to access the array, the access will be terminated with an
error This causes a machine check exception for the RCPU.
If S = 0, the RAM array is placed in Unrestricted Space and access by both Supervisor
and User programs is allowed.
These bits can be set in Factory test mode only. The User should treat these bits as
reserved and always write as zeros.
Reserved
Burst Enable
0 Burst access is disabled.
1 Burst access is enabled.
20
4
0
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 4-4. BBCMCR Field Descriptions
COMP
ID21
EN_
21
5
2
1
EXC_COMP
TEST
ID22
22
6
0000_0000_0000_0000
2
1
SPR 560
DECOMP_SC_
ID21
EN
23
7
Description
1
2
OERC[0:1] BTEE
ID(24:25)
24
8
25
9
2
Burst Buffer Controller 2 Module
10
26
Section 7.5.2, “Hard Reset
—
11 12 13
27 28 29
00_0000
—
DCAE TST
14
30
LSB
15
31
4-19