MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 205

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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detected and data storage interrupt is never generated by the hardware. In the RCPU, the instruction can
be partially executed only in the case of the load/store instructions that cause multiple accesses to the
memory subsystem. These instructions are:
In the last case, the store instruction can be partially completed if one of the accesses (except the first one)
causes the data storage protection error. The implementation-specific data storage protection interrupt is
taken in this case. For the update forms, the update register (rA) is not altered.
3.15.6
Descriptions of the timebase and decrementer registers can be found in
and
3.15.7
Any other OEA optional facilities and instructions (except those that are discussed here) are not
implemented by the RCPU hardware. Attempting to execute any of these instructions causes an
implementation dependent software emulation interrupt to be taken.
Freescale Semiconductor
Protection,” and in
Multiple/string instructions
Unaligned load/store instructions
Timer Facilities
Optional Facilities and Instructions
Chapter 8, “Clocks and Power
MPC561/MPC563 Reference Manual, Rev. 1.2
Control.”
Chapter 6, “System Configuration
Central Processing Unit
3-61

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