MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1089
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
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Appendix A
MPC562/MPC564 Compression Features
The MPC562/MPC564 contains a number of code compression features not found in the
MPC561/MPC563 that function from the burst buffer controller module (BBC) module of the device.
The BBC’s instruction code decompressor unit (ICDU) is responsible for on-line (previously compressed)
instruction code decompression in the decompression on mode. The ICDU contains a 2-Kbyte RAM
(DECRAM) that is used for decompressor vocabulary table storage when compression is enabled or as
general-purpose memory on the U-bus when compression is disabled.
A.1
The following are instruction code decompression unit key features:
A.2
The operational model used by the MPC562/MPC564 is explained in the sections below.
A.2.1
Freescale Semiconductor
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Instruction code on-line decompression is based on an “instruction class” algorithm.
There is no need for address translation between compressed and non-compressed address spaces
— ICDU provides the “next instruction address” to the RCPU.
In most cases, instruction decompression takes one clock.
Code decompression is pipelined:
— No performance penalty during sequential program flow execution
— Minimal performance penalty due to change of program flow execution
Two operation modes are available: decompression on and decompression off. Switches between
compressed and non-compressed user application software is possible.
Adaptive vocabularies scheme is supported; each user application can have its own optimum
vocabularies.
Implemented for MPC56x architecture
Up to 50% instruction code size reduction
No need for address translation tables
ICDU Key Features
Class-Based Compression Model Main Principles
Compression Model Features
The code compression features of the MPC562/MPC564 are different than
the code compression of the MPC556.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
A-1
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