MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1099

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

A.2.9.5
This MPC562/MPC564 instruction is divided into two segments. The left segment is either fully bypassed
by a 16-bit field or by a shorter field which is decompressed according to fixed rules. The right segment
is compressed and mapped into a vocabulary. The vocabulary location is programmable. The compressed
fields must be swapped in the compressed instruction order to follow the rule that bypass appears only in
the second field of a compressed instruction.
The definition of the class includes:
When the vocabulary is located in RAM #1, the class is referred to as CLASS_4band when the vocabulary
is located in RAM #2, the class is referred to as CLASS_4a. Refer to
A.2.10
Table A-4
The un-compressed instruction of two half-words are referred as H1 & H2. The compressed instruction
can be built out of: (1) X1 field – representing a vocabulary pointer for encoding of either H1 or H1+H2;
(2) X2 field – representing a vocabulary pointer for encoding of H2; and (3) BP – representing a bypass
field.
Vocabularies V1 and V2 refer to the 16 MSB and 16 LSB of the uncompressed instruction, respectively.
A.2.11
The compression process is implemented by the following steps. See
Freescale Semiconductor
.
MSB
•
•
•
•
•
•
•
•
•
16-bit segment #1 – to be bypassed
4-bit class
TP1 length=2-9
TP2 length=0xB, 0xC, 0xD, or 0xE indicating a 0, 10, 15 or 16 bit bypass, respectively.
TP1 base address = base address of segment #1 vocabulary in RAM #1, if it exists there
TP2 base address = base address of segment #1 vocabulary in RAM #2, if it exists there
DS=1
AS=0 or 1 directing access to the vocabulary in RAM #1 or RAM #2, respectively.
User code compilation/linking
Vocabulary and class generation
User application code compression by a software compression tool
summarizes the programming for all possible compressed instruction layouts.
Instruction Layout Programming Summary
Compression Process
Left Segment Bypass and Right Segment Compression—CLASS_4
2- to 9-bit TP1 for segment #2
Figure A-10. CLASS_4 Instruction Layout
MPC561/MPC563 Reference Manual, Rev. 1.2
Uncompressed Instruction
Compressed Instruction
16-bit segment #2 – to be compressed
0-, 10-, 15- or 16-bit bypass for segment #1
Table
Figure
MPC562/MPC564 Compression Features
A-4.
A-11.
A-11