EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 1000

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–42
Table 1–12. MegaWizard Plug-In Manager Options (Word Aligner Screen) (Part 4 of 4)
Stratix IV Device Handbook Volume 3
Create an rx_invpolarity
port to enable word aligner
polarity inversion.
Create an
rx_revbyteorderwa to
enable Receiver symbol swap.
Create
rx_bitslipboundaryselec
tout port to indicate the
number of bits slipped in the
word aligner.
ALTGX Setting
This optional port allows you to dynamically reverse
the polarity of every bit of the received data at the
input of the word aligner. Use this option when the
positive and negative signals of the differential input to
the receiver (rx_datain) are erroneously swapped on
the board.
This is an optional input port that is available only in
the double-width mode. It creates an
rx_revbyteorderwa port to dynamically swap the
MSByte and LSByte of the data at the output of the
word aligner in the receiver data path. Enabling this
option compensates for the erroneous swapping of
bytes at the upstream transmitter and corrects the
data received by the downstream systems.
For example, if the 16-bit output of the word aligner is
0B0A, asserting the rx_revbyteorderwa signal
swaps the two bytes so the output becomes 0A0B.
This option is available for selection only when you are
in Receiver only or Receiver and Transmitter
operation mode. This option enables the
rx_bitslipboundaryselectout output to indicate
the number of bits slipped in the word aligner.
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“Receiver Polarity Inversion”
section in the
Architecture in Stratix IV Devices
chapter.
“Receiver Byte Reversal in Basic
Double-Width Modes” section in
the
Stratix IV Devices
Transceiver Architecture in
February 2011 Altera Corporation
Reference
Transceiver
—
chapter.
Protocol Settings