EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 707

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Figure 2–21. Transmitter Channel PMA Directly Interfacing to the User Logic in the FPGA Fabric
Note to
(1) The green lines represent the low-speed parallel clock and the blue lines represent the high-speed serial clock.
February 2011 Altera Corporation
Figure
2–21:
1
FPGA
Fabric
Stratix IV devices do not allow the 6G ATX PLL to generate transceiver clocks in
non-bonded Basic (PMA Direct) mode. The transmitter clock for channels configured
in non-bonded Basic (PMA Direct) mode must be generated by one of the CMU PLLs
in the transceiver block containing the channels.
tx_clkout[3]
tx_clkout[2]
tx_clkout[1]
tx_clkout[0]
CMU0_PLL
Divider
CMU1
Divider
CMU0
Clock
Clock
CMU1_Channel
Low-Speed Parallel Clock
Transmitter Channel PCS
Low-Speed Parallel Clock
Transmitter Channel PCS
Low-Speed Parallel Clock
Transmitter Channel PCS
Low-Speed Parallel Clock
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
CMU0_Channel
Channel 1
Channel 0
Channel 3
Channel 2
Stratix IV Device Handbook Volume 2: Transceivers
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Divider Block
Divider Block
Divider Block
Divider Block
Local Clock
Local Clock
Local Clock
Local Clock
Serializer
Serializer
Serializer
Serializer
Serializer
x1 High-Speed Serial Clock
x1 High-Speed Serial Clock
x1 High-Speed Serial Clock
x1 High-Speed Serial Clock
(Note 1)
2–35