EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 832

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–26
Figure 4–14. Identical Channels
Stratix IV Device Handbook Volume 2: Transceivers
locked
Transmitter Side User Logic
in the FPGA Fabric
Transmitter Only Channel with a PLL_L/R
The Basic (PMA Direct) mode configuration that requires a PLL_L/R is one where
each channel in PMA-Direct mode is identical.
identical channels.
c0
Identical channels have the following same configuration:
■
■
■
■
Figure 4–15
Only channels in Basic (PMA Direct) Drive x4 functional mode with a PLL_L/R.
As shown in
Drive functional mode with a PLL_L/R configuration, follow these reset steps:
1. After power up, assert pll_powerdown for a minimum of t
2. After the transmitter PLL locks, as indicated by the pll_locked signal going high
3. After the PLL_L/R locks, as indicated by the locked signal going high (marker 4),
Same effective data rate
Same transmitter local clock divider settings in each channel
Same FPGA fabric-to-transceiver interface data path width
The transmitter channels must receive the high-speed clock from the same PLL
(either CMU PLL or ATX PLL).
between markers 1 and 2).
(marker 3), wait for the locked signal to be asserted. The locked signal is an output
of the PLL_L/R.
the transmitter is ready to accept parallel data from the FPGA fabric and
subsequently transmitting serial data reliably.
Left and Right PLL
(ALTPLL)
shows an example reset sequence timing diagram of four Transmitter
Figure
tx_datain[9:0]
inclk0
4–15, for the Transmitter Only channel in Basic (PMA Direct)
pll_locked
tx_clkout
refclk
Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transmitter Channels in Basic
CMU Channel configured
for clock generation
(PMA Direct) Mode
CH0 (2.5 Gbps)
CH2 (2.5 Gbps)
CH1 (2.5 Gbps)
CH3 (2.5 Gbps)
Figure 4–14
(2.5 Gbps)
PMA Direct Drive Mode Reset Sequences
shows a simple set up of
February 2011 Altera Corporation
pll_powerdown
High-Speed
Serial Clock
(the time