EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 836

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–30
Figure 4–17. Reset Sequence with CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
(3) For t
Stratix IV Device Handbook Volume 2: Transceivers
Figure
pll_powerdown
LTR_LTD_Manual
LTD_Manual
Reset and Power Down Signals
4–17:
duration, refer to the
duration, refer to the
duration, refer to the
Ouput Status Signals
CDR Control Signals
rx_analogreset[0]
rx_analogreset[3]
Receiver and Transmitter Channel Set-up—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. For PMA Direct
drive ×N mode, with receiver CDR in manual lock mode, use the reset sequence
shown in
pll_powerdown
rx_locktorefclk[3]
rx_locktorefclk[0]
rx_dataout[63:0]
rx_locktodata[0]
rx_locktodata[3]
rx_pll_locked[0]
rx_pll_locked[3]
pll_locked
busy
DC and Switching Characteristics for Stratix IV Devices
Figure
DC and Switching Characteristics for Stratix IV Devices
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
4–17. In this example, N = 4.
2
3
Minimum of Two Parallel Clock Cycles
4
5
5
t
6
6
LTR_LTD_Manual (2)
Chapter 4: Reset Control and Power Down in Stratix IV Devices
7
7
7
7
t
LTD_Manual (3)
chapter.
chapter.
chapter.
8
PMA Direct Drive Mode Reset Sequences
valid parallel data into FPGA fabric
February 2011 Altera Corporation