EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 201
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
February 2011 Altera Corporation
Expanded On-Chip Series Termination with Calibration
OCT calibration circuits always adjust OCT R
connected to the RUP and RDN pin; however, it is possible to achieve OCT R
other than the 25-Ω and 50-Ω resistors. Theoretically, if you need a different OCT R
value, you can change the resistance connected to the RUP and RDN pins accordingly.
Practically, the OCT R
output buffer size and granularity limitations.
The Quartus II software only allows discrete OCT R
and 60 Ω . You can select the closest discrete value of OCT R
in the Quartus II software to your system to achieve the closest timing. For example, if
you are using 20-Ω OCT R
OCT R
timing.
Table 6–8
expanded on-chip series termination with calibration of SSTL and HSTL for
impedance matching to improve signal integrity but do not use it to meet the JEDEC
standard.
Table 6–8. Selectable I/O Standards with Expanded On-Chip Series Termination with Calibration
Range
Dynamic On-Chip Termination
Stratix IV devices support on and off dynamic termination, both series and parallel,
for a bidirectional I/O in all I/O banks.
supported in Stratix IV devices. Dynamic parallel termination is enabled only when
the bidirectional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic series termination is enabled only when the bidirectional I/O acts
as a driver and is disabled when it acts as a receiver. This feature is useful for
terminating any high-performance bidirectional path because signal integrity is
optimized depending on the direction of the data.
Using dynamic OCT helps save power because device termination is internal instead
of external. Termination only switches on during input operation, thus drawing less
static power.
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
1.2-V LVTTL/LVCMOS
SSTL-2
SSTL-18
SSTL-15
HSTL-18
HSTL-15
HSTL-12
S
with calibration setting in the Quartus II software to achieve the closest
I/O Standard
lists expanded OCT R
S
range that Stratix IV devices support is limited because of
S
with calibration in your system, you can select the 25-Ω
S
with calibration supported in Stratix IV devices. Use
Row I/O (Ω)
Figure 6–21
20–60
20–60
20–60
40–60
40–60
20–60
20–60
40–60
20–60
40–60
40–60
S
Expanded OCT R
to match the external resistors
S
shows the termination schemes
calibration settings of 25, 40, 50,
Stratix IV Device Handbook Volume 1
S
with calibration settings
S
Range
Column I/O (Ω)
20–60
20–60
20–60
20–60
20–60
20–60
20–60
20–60
20–60
20–60
20–60
S
values
6–29
S
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