EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 415

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 11: SEU Mitigation in Stratix IV Devices
Error Detection Timing
February 2011 Altera Corporation
1
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (refer to
in which n is between 1 and 8. The divisor ranges from 2 through 256. Refer to
Equation
Equation 11–1.
The error detection frequency reflects the frequency of the error detection process for
a frame because the CRC calculation in the Stratix IV device is done on a per-frame
basis.
You must monitor the error message to avoid missing information in the error
message register. The error message register is updated whenever an error occurs. The
minimum interval time between each update for the error message register depends
on the device and the error detection clock frequency.
Table 11–6
error message register for Stratix IV devices.
Table 11–6. Minimum Update Interval for Error Message Register
CRC calculation time for the error detection circuitry to check from the first until the
last frame depends on the device and the error detection clock frequency.
Note to
(1) These timing numbers are preliminary.
Table
11–1.
lists the estimated minimum interval time between each update for the
11–6:
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
EP4SGX70
EP4S40G2
EP4S40G5
EP4SE230
EP4SE360
EP4SE530
EP4SE820
“Software Support” on page
Device
error detection frequency
11–10). The divisor is a power of two,
=
100 MHz
----------------------- -
2
n
Timing Interval (μs)
Stratix IV Device Handbook Volume 1
(Note 1)
13.8
13.8
19.8
19.8
21.8
21.8
26.8
19.8
21.8
26.8
33.8
19.8
26.8
19.8
26.8
26.8
26.8
11–9