EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 631

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–153. Rate Match FIFO Deletion with One Skip Pattern Inserted
February 2011 Altera Corporation
dataout
datain
f
1
K28.5
K28.5
First Skip Cluster
Figure 1–153
skip pattern is required to be inserted. In this example, the first skip cluster has a
/K28.5/ control pattern followed by three /K29.7/ skip patterns. The second skip
cluster has a /K28.5/ control pattern followed by two /K29.7/ skip patterns. The rate
match FIFO inserts only one /K29.7/ skip pattern into the first skip cluster. One
/K29.7/ skip pattern is inserted into the second cluster.
Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to
indicate rate match FIFO full and empty conditions. For more information about the
behavior of these two signals, refer to
on page
Basic (PMA Direct) Functional Mode
In Basic (PMA Direct) functional mode, the Stratix IV GX and GT transceiver datapath
contains only PMA blocks. Parallel data is transferred directly between the FPGA
fabric and the serializer/deserializer inside the transmitter/receiver PMA. Because all
PCS blocks are bypassed in Basic (PMA Direct) mode, you must implement the
required PCS logic in the FPGA fabric.
You can configure four regular transceiver channels inside each transceiver block in
Basic (PMA Direct) functional mode. You can configure two CMU channels inside
each transceiver block only in Basic (PMA Direct) functional mode, as they do not
support PCS circuitry.
In PMA Direct mode, you must create your own logic to support PCS functionality.
There are specific reset sequences to be followed in this mode.
Use dynamic reconfiguration to dynamically reconfigure the various PMA controls to
tailor the transceivers in PMA direct drive mode for a particular application.
For more information, refer to the
chapter. For more information about the reset sequence to follow in PMA-Direct
mode, refer to the
The term ‘PMA-Direct’ is used to describe various configurations in this mode.
In Basic (PMA Direct) mode, all the PCS blocks are bypassed; therefore, any PCS-type
features (for example, phase compensation FIFOs, byte serializer, 8B/10B
encoder/decoder, word aligner, deskew FIFO, rate match FIFO, byte deserializer, and
byte ordering), must be implemented in the FPGA fabric. In Basic (PMA Direct) mode,
you must create your own logic to support PCS functionality.
K29.7
K29.7
1–84.
K29.7
K29.7
shows an example of rate match FIFO insertion in the case where one
Reset Control and Power Down in Stratix IV Devices
K29.7
K29.7
One Skip Pattern Inserted
K29.7
K28.5
Dynamic Reconfiguration in Stratix IV Devices
Second Skip Cluster
“Rate Match FIFO in Basic Single-Width Mode”
K29.7
K28.5
K29.7
K29.7
Stratix IV Device Handbook Volume 2: Transceivers
Dx.y
K29.7
K29.7
chapter.
Dx.y
1–187