EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 557

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–94. Transceiver Configurations in Basic Single-Width Mode with an 8-Bit PMA-PCS Interface for Stratix IV GX
Devices
Note to
(1) The maximum data rate specification shown in
February 2011 Altera Corporation
other speed grades offered, refer to the
Figure
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
(1)
(1)
TX PCS Latency
Interface Frequency
RX PCS Latency
1–94:
Interface Frequency
Interface Frequency
Fabric-Transceiver
Fabric-Transceiver
Low-Latency PCS
Rate Match FIFO
Data Rate (Gbps)
Encoder/Decoder
Data Rate (Gbps)
Channel Bonding
Interface Width
(Pattern Length)
Interface Width
FPGA Fabric -
FPGA Fabric
Byte Ordering
Byte SerDes
Word Aligner
Transceiver
Transceiver
Interface Width
PMA-PCS
Functional
FPGA
(MHz)
PMA-PCS
8B/10B
FPGA
Modes
Basic Single-Width Mode Configurations
Figure 1–94
single-width functional mode with an 8-bit PMA-PCS interface.
Figure 1–95
single-width functional mode with an 8-bit PMA-PCS interface.
8-bit
Disabled
Disabled
Single
Width
11-13
8-Bit
0.6 -
75 -
5 -6
DC and Switching Characteristics
2.0
250
shows Stratix IV GX transceiver configurations allowed in Basic
shows Stratix IV GT transceiver configurations allowed in Basic
Manual Alignment
10-Bit
Disabled
Disabled
(16-Bit)
Basic
Figure 1–94
195.3125
Disabled
4 - 5.5
16-Bit
16-Bit
37.5 -
7 - 9
Enabled
Double
Width
3.125
0.6 -
Disabled
195.3125
20-Bit
Enabled
16-Bit
4 - 5.5
37.5 -
Stratix IV GX Configurations
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
7 - 9
10-Bit
PIPE
Disabled
Disabled
11 - 13
8-Bit
0.6 -
75 -
5 -6
2.0
250
chapter.
Disabled
Disabled
Bit-Slip
(16-Bit)
10-Bit
XAUI
Basic Single-Width
8-Bit PMA-PCS
Interface Width
195.3125
Enabled
Disabled
x1, x4, x8
4 - 5.5
16-Bit
0.6 - 3.2
37.5 -
3.125
0.6 -
7 - 9
GIGE
10-Bit
Protocol
SRIO
10-Bit
Stratix IV Device Handbook Volume 2: Transceivers
SONET
/SDH
8-Bit
16-Bit
(OIF)
CEI
10-Bit
SDI
Disabled
Disabled
8-Bit
0.6 -
4 - 5
3 - 4
75 -
250
2.0
Disabled
Disabled
Disabled
Enabled
10
Deterministic
-Bit
Latency
Disabled
Enabled
16-Bit
37.5 -
4 - 5.5
3 - 4.5
200
0.6 -
3.2
20-Bit
1–113