EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 1032

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–14
Guidelines to Debug Transceiver-Based Designs
Stratix IV Device Handbook Volume 3
f
In the Compile to library option, select the corresponding library for the file selected.
Figure 2–2
the Stratix II GX device.
Figure 2–2. ModelSim Option to Compile Files in a Specific Library
Include all the libraries in the search path. Add the ALTGX and ALTGX_RECONFIG
MegaWizard Plug-In Manager-generated wrapper files (.v or .vhd) and all of the
design files to the library. Compile all the library files first, then the design files, and
lastly run the simulation.
For Verilog simulation, add the ALTGX and ALTGX_RECONFIG MegaWizard
Plug-In Manager-generated Verilog wrapper files (.v), the Altera library files, and all
of the design files. Compile all the library files first, then the simulation model file,
followed by the design files. Lastly, run the simulation.
These guidelines are further described in
Application”
For more information about functional register transfer level (RTL) simulation or
post-fit simulation, refer to the
Handbook.
This section provides guidelines to debug transceiver-based designs. If a system
failure occurs, the first step is to ensure the functionality of the logic within the FPGA.
Use the following information when you observe a system failure.
shows the ModelSim window compilation of files in a specific library for
below.
Simulation
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
“Example 1: Fibre Channel Protocol
chapter in volume 3 of the Quartus II
Guidelines to Debug Transceiver-Based Designs
February 2011 Altera Corporation