EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 1047

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
Figure 2–12. FC4G Instance Settings (Word Aligner Screen)
February 2011 Altera Corporation
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Word Aligner screen—The fibre channel protocol requires that you use K28.5 to
align the byte boundary. In the What is the word alignment pattern? option, set
one of the 10-bit disparity values to K28.5. The word aligner automatically detects
when the other disparity value is received.
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Select the rx_patterndetect and rx_syncstatus signals. The
rx_patterndetect signal indicates whenever the word alignment pattern is
detected in the word boundary.
Click Finish to exit the ALTGX MegaWizard Plug-In Manager.
Stratix IV Device Handbook Volume 3
2–29