EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 579

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–111. Compliance Pattern Transmission Support, 8-Bit Channel Width Configurations
Figure 1–112. Compliance Pattern Transmission Support, 16-Bit Wide Channel Configurations
February 2011 Altera Corporation
tx_forcedispcompliance
tx_forcedispcompliance[1:0]
tx_datain[7:0]
tx_ctrlenable[1:0]
tx_ctrlenable
tx_datain[15:0]
The PCIe protocol requires the first /K28.5/ code group of the compliance pattern to
be encoded with negative current disparity. To satisfy this requirement, the PCIe
interface block provides the input signal tx_forcedispcompliance. A high level on
tx_forcedispcompliance forces the associated parallel transmitter data on the
tx_datain port to transmit with negative current running disparity.
■
■
Figure 1–111
tx_forcedispcompliance signal while transmitting the compliance pattern in 8-bit
and 16-bit channel width configurations, respectively.
The PCIe specification defines four power states—P0, P0s, P1, and P2—that the
physical layer device must support to minimize power consumption.
■
■
For 8-bit transceiver channel width configurations, you must drive
tx_forcedispcompliance high in the same parallel clock cycle as the first /K28.5/
of the compliance pattern on the tx_datain port.
For 16-bit transceiver channel width configurations, you must drive only the LSB
of tx_forcedispcompliance[1:0] high in the same parallel clock cycle as
/K28.5/D21.5/ of the compliance pattern on the tx_datain port.
P0 is the normal operating state during which packet data is transferred on the
PCIe link.
P0s, P1, and P2 are low-power states into which the physical layer must transition
as directed by the PHY-MAC layer to minimize power consumption.
Power State Management
K28.5
BC
and
/K28.5/D21.5/
B5BC
Figure 1–112
01
D21.5
B5
K28.5
BC
show the required level on the
/K28.5/D10.2/
BC4A
00
D10.2
4A
01
K28.5
BC
/K28.5/D21.5/
Stratix IV Device Handbook Volume 2: Transceivers
B5BC
D21.5
B5
K28.5
BC
/K28.5/D10.2/
BC4A
D10.2
4A
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