EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 220

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–48
Document Revision History
Table 6–13. Document Revision History
Stratix IV Device Handbook Volume 1
February 2011
March 2010
November 2009
June 2009
April 2009
March 2009
November 2008
May 2008
Date
Version
Table 6–13
3.0
2.0
3.2
3.1
2.3
2.2
2.1
1.0
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Initial release.
Updated the
Schemes”,
sections.
Updated
Applied new template.
Minor text edits.
Updated Table 6–2 and Table 6–5.
Updated Figure 6–18, Figure 6–19, Figure 6–27, Figure 6–28, and Figure 6–31.
Added the “Summary of OCT Assignments” section.
Added a note to the “Sharing an OCT Calibration Block on Multiple I/O Banks” section.
Updated the “OCT Calibration” section.
Minor text edits.
Updated Table 6–2, Table 6–4, Table 6–6, Table 6–9, and Table 6–10.
Updated Figure 6–1, Figure 6–2, Figure 6–4, Figure 6–5, Figure 6–6, Figure 6–8,
Figure 6–9, Figure 6–10, Figure 6–11, Figure 6–12, Figure 6–13, and Figure 6–31.
Added Table 6–8.
Added Figure 6–7, Figure 6–14, Figure 6–15, and Figure 6–16.
Added “Left-Shift Series Termination Control” and “Expanded On-Chip Series Termination
with Calibration” sections.
Updated “MultiVolt I/O Interface”, “RSDS”, “Mini-LVDS”, and “Non-Voltage-Referenced
Standards” sections.
Deleted Figure 6-5: Number of I/Os in Each Bank in EP4SE290 and EP4SE360 in the
1517-Pin FineLine BGA Package.
Minor text edits.
Added introductory sentences to improve search ability.
Removed the Conclusion section.
Updated Figure 6–2.
Updated Table 6–8 and Table 6–9.
Deleted Figure 6-14.
Updated Table 6–1, Table 6–2,Table 6–3, Table 6–4, Table 6–6, Table 6–8, and Table 6–9.
Updated Figure 6–2, Figure 6–7, Figure 6–8, Figure 6–9, Figure 6–10, Figure 6–11, and
Figure 6–12.
Added Figure 6–14.
Removed Equation 6–2 and “Referenced Documents” section.
Updated “Modular I/O Banks” on page 6–7.
Updated Figure 6–3 and Figure 6–21.
Made minor editorial changes.
lists the revision history for this chapter.
Figure
“Dynamic On-Chip
“Modular I/O
6–17,
Figure 6–32
Banks”,
Termination”, and
“On-Chip Termination Support and I/O Termination
and
Changes
Figure
6–33.
“Programmable Pull-Up Resistor”
Chapter 6: I/O Features in Stratix IV Devices
February 2011 Altera Corporation
Document Revision History