EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 685
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
Figure 2–8. FPGA Fabric PLLs-Transceiver PLLs Cascading Options Allowed in the 1932-Pin Package Device
February 2011 Altera Corporation
FPGA Fabric PLLs-Transceiver PLLs Cascading in the 1932-Pin Package
Transceiver Block GXBL2
Channel 2
Channel 3
Transceiver Block GXBL0
Channel 3
Channel 2
Channel 2
Transceiver Block GXBL1
Channel 3
Channel 1
Channel 0
Channel 1
Channel 0
Transceiver Block GXBL3
Channel 3
Channel 1
Channel 0
Channel 1
Channel 0
Channel 2
ATX PLL L1 (6G)
ATX PLL L0 (6G)
1
CMU1
CMU0
CMU1
CMU0
CDR
CMU1
CMU0
CMU1
CMU0
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Figure 2–8
in the EP4SGX530NF45, EP4SGX360NF45, and EP4SGX290NF45 devices.
For Stratix IV GT devices, FPGA fabric PLLs-Transceiver PLLs cascading is not
supported for the 10G ATX PLLs. For the EP4S100G3NF45, EP4S100G4N45, and
EP4S100G5NF45 devices, FPGA fabric PLLs-Transceiver PLLs cascading for the
6G ATX PLLs and CMU PLLs is the same as the Stratix IV GX devices in the 1932-pin
package.
Cascade
Network
PLL
shows the FPGA fabric PLLs-Transceiver PLLs cascading options allowed
PLL_L4
PLL_L1
PLL_L2
PLL_L3
EP4SGX530NF45
EP4SGX360NF45
EP4SGX290NF45
PLL_R2
PLL_R3
PLL_R1
PLL_R4
Stratix IV Device Handbook Volume 2: Transceivers
Cascade
Network
PLL
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR0
Transceiver Block GXBR1
ATX PLL R0 (6G)
ATX PLL R1 (6G)
CMU1
CMU1
CMU1
CMU0
CMU0
CMU1
CMU0
CDR
CMU0
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Channel 1
Channel 3
Channel 3
Channel 2
Channel 1
Channel 3
Channel 2
Channel 0
Channel 3
Channel 2
Channel 0
Channel 2
Channel 1
Channel 1
Channel 0
Channel 0
2–13
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