EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 665

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Table 1–77. Stratix IV GX and GT ALTGX Megafunction Ports: PCIe Interface (Part 2 of 4)
February 2011 Altera Corporation
tx_pipemargin
tx_pipedeemph
pipe8b10binvpolarity
Port Name
Output
Input/
Input
Input
Input
Clock Domain
Asynchronous
Asynchronous
Asynchronous
signal
signal
signal
Transmitter differential output voltage level control.
■
■
■
Transmitter buffer de-emphasis level control.
■
■
■
■
PCIe polarity inversion control.
■
■
■
Functionally equivalent to the txmargin signal
defined in the PCIe specification revision 2.0.
Available only in PCIe Gen2 configuration.
The width of this signal is 3 bits and is decoded
as follows:
■
■
■
■
■
■
■
■
Functionally equivalent to the txdeemph signal
defined in the PCIe specification revision 2.0.
Available only in PCIe Gen2 configuration.
1’b0: -6 dB de-emphasis
1’b1:-3.5 dB de-emphasis
Functionally equivalent to the rxpolarity
signal defined in the PCIe specification revision
2.0.
Available only in PCIe mode.
When asserted high—the polarity of every bit of
the 10-bit input data to the 8B/10B decoder gets
inverted.
3’b000—Normal Operating Range
3’b001—Full Swing = 800 - 1200 mV
3’b010—TBD
3’b011—TBD
3’b100—If last value, full Swing = 200 to 400
mV
3’b101—If last value, full Swing = 200 to 400
mV
3’b110—If last value, full Swing = 200 to 400
mV
3’b111—If last value, full Swing = 200 to 400
mV
Stratix IV Device Handbook Volume 2: Transceivers
Description
1–221
Channel
Scope