EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 132

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–16
Stratix IV Device Handbook Volume 1
f
1
You can set the input clock sources and the clkena signals for the GCLK and RCLK
network multiplexers through the Quartus II software using the ALTCLKCTRL
megafunction. You can also enable or disable the dedicated external clock output pins
using the ALTCLKCTRL megafunction.
clock control block.
When using the ALTCLKCTRL megafunction to implement dynamic clock source
selection, the inputs from the clock pins feed the inclk[0..1] ports of the multiplexer,
while the PLL outputs feed the inclk[2..3] ports. You can choose from among these
inputs using the CLKSELECT[1..0] signal.
For more information, refer to the
User
Figure 5–13. Stratix IV External PLL Output Clock Control Block
Notes to
(1) When the device is operation in user mode, you can only set the clock select signals through a configuration file (.sof
(2) The clock control block feeds to a multiplexer within the PLL_<#>_CLKOUT pin’s IOE. The PLL_<#>_CLKOUT
or .pof) and cannot be dynamically controlled.
pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control
block.
Guide.
Figure
5–13:
IOE
Internal
Logic
(2)
PLL_<#>_CLKOUT pin
7 or 10
Clock Control Block (ALTCLKCTRL) Megafunction
PLL Counter
Outputs
Enable/
Disable
Figure 5–13
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Internal
Static Clock
Select (1)
Logic
Static Clock Select
shows the external PLL output
(1)
Clock Networks in Stratix IV Devices
February 2011 Altera Corporation