EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 497

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–45. Clock and Data Recovery Unit
Note to
(1) The blue colored path is active in lock-to-reference mode; the red colored path is active in lock-to-data mode.
February 2011 Altera Corporation
rx_datain
rx_locktorefclk
rx_freqlocked
rx_locktodata
Figure
signal detect
rx_cruclk
1–45:
1
/1, /2, /4
Clock and Data Recovery Unit
Each Stratix IV GX and GT receiver channel has an independent CDR unit to recover
the clock from the incoming serial data stream. The high-speed and low-speed
recovered clocks are used to clock the receiver PMA and PCS blocks.
shows the CDR block diagram.
The CDR operates either in LTR mode or LTD mode. In LTR mode, the CDR tracks the
input reference clock. In LTD mode, the CDR tracks the incoming serial data.
After the receiver power up and reset cycle, the CDR must be kept in LTR mode until
it locks to the input reference clock. After it is locked to the input reference clock, the
CDR output clock is trained to the configured data rate. The CDR can now switch to
LTD mode to recover the clock from incoming data. The LTR/LTD controller controls
the switch between LTR and LTD modes.
In LTR mode, the phase frequency detector in the CDR tracks the receiver input
reference clock, rx_cruclk. The PFD controls the charge pump that tunes the VCO in
the CDR. Depending on the data rate and the selected input reference clock frequency,
the Quartus II software automatically selects the appropriate /M and /L divider
values such that the CDR output clock frequency is half the data rate. An active high,
the rx_pll_locked status signal is asserted to indicate that the CDR has locked to the
phase and frequency of the receiver input reference clock.
shows the active blocks (in blue) when the CDR is in LTR mode.
The phase detector (PD) is inactive in LTR mode.
Lock-to-Reference (LTR) Mode
/2
LTR/LTD
Controller
Frequency
Detector
Detector
Phase
Phase
(PFD)
(PD)
(Note 1)
Down
Up
Up
Down
Charge Pump
Loop Filter
+
Clock and Data Recovery (CDR) Unit
VCO
Stratix IV Device Handbook Volume 2: Transceivers
/2
/M
Figure 1–45 on page 1–53
/L
Figure 1–45
Recovered Clock
Recovered Clock
rx_pll_locked
High-Speed
Low-Speed
1–53