EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 513

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–31. Word Aligner Options Available in Basic Single-Width and Double-Width Modes
February 2011 Altera Corporation
Basic
Single-Width
Functional
Mode
PMA-PCS
Interface
Width
10-bit
8-bit
Table 1–31
double-width modes.
Word Alignment
Synchronization
State Machine
Alignment
Alignment
Automatic
Manual
Bit-Slip
Manual
Bit-Slip
Mode
lists the word aligner options available in Basic single-width and
7- and 10-bit
7- and 10-bit
7- and 10-bit
Alignment
Pattern
Length
16-bit
16-bit
Word
rx_enapatternalign
Level Sensitive
Rising Edge
Sensitivity
Sensitive
N/A
N/A
N/A
Stratix IV Device Handbook Volume 2: Transceivers
Asserted high for
one parallel clock
cycle when the
word aligner
aligns to a new
word boundary.
Asserted high for
one parallel clock
cycle when the
word aligner
aligns to a new
word boundary.
Stays high as
long as the
synchronization
conditions are
satisfied.
rx_syncstatus
Behavior
N/A
N/A
(Note 1)
(Part 1 of 2)
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
rx_patterndetect
Behavior
1–69