EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 410

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

11–4
Table 11–2. Fault Injection Register
Stratix IV Device Handbook Volume 1
Content
Note to
(1) Bit[20] and Bit[19] cannot both be set to 1 as this is not a valid selection. The error detection circuitry decodes this as no error injection.
Description
Bit
Table
11–2:
1
1
Bit[20]
Error Type
0
1
0
A JTAG instruction, EDERROR_INJECT, is provided to test the capability of the error
detection block. This instruction is able to change the content of the 21-bit JTAG fault
injection register that is used for error injection in Stratix IV devices, enabling the
testing of the error detection block.
You can only execute the EDERROR_INJECT JTAG instruction when the device is in user
mode.
Table 11–1
Table 11–1. EDERROR_INJECT JTAG Instruction
You can create a Jam™ file (.jam) to automate the testing and verification process.
This allows you to verify the CRC functionality in-system, on-the-fly, without having
to reconfigure the device. You can then switch to the CRC circuit to check for real
errors induced by an SEU.
You can introduce a single-error or double-errors adjacent to each other to the
configuration memory. This provides an extra way to facilitate design verification and
system fault tolerance characterization. Use the JTAG fault injection register with the
EDERROR_INJECT instruction to flip the readback bits. The Stratix IV device is then
forced into error test mode.
The content of the JTAG fault injection register is not loaded into the fault injection
register during the processing of the last and first frame. It is only loaded at the end of
this period.
You can only introduce error injection in the first data frame, but you can monitor the
error information at any time. For more information about the JTAG fault injection
register and fault injection register, refer to
Table 11–2
injection.
EDERROR_INJECT
JTAG Instruction
Bit[19]
(1)
1
0
0
lists the description of the EDERROR_INJECT JTAG instruction.
lists how the fault injection register is implemented and describes error
Error injection type
Single-byte error injection
Double-adjacent byte error injection
No error injection
Bit[20..19]
Error Type
Instruction Code
00 0001 0101
“Error Detection Registers” on page
This instruction controls the 21-bit JTAG fault
injection register, which is used for error
injection.
Depicts the location
of the injected error
in the first data
frame.
the Injected Error
Chapter 11: SEU Mitigation in Stratix IV Devices
Byte Location of
Bit[18..8]
Description
February 2011 Altera Corporation
User Mode Error Detection
Depicts the location
of the bit error and
corresponds to the
error injection type
selection.
Error Byte Value
Bit[7..0]
11–7.