EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 907

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–31. Input Reference Clocks Connections to the Transceiver Channels
Note to
(1) Depending on the mode you select, the PCS unit may or may not be present.
February 2011 Altera Corporation
Figure
5–31:
(Identification
number = 2)
(Identification
number = 1)
Refclk0
Refclk1
156 .25 MHz
125MHz
Figure 5–31
to the transceiver channels are based on what you set as the input clock source for
each of the CMU transmitter PLLs within a transceiver block.
Based on what you have set up
selects the corresponding input
as the input clock source for
clock source for CMU0 PLL.
CMU0 PLL, this clock mux
shows an example scenario where the input reference clock connections
Based on what you have set up
selects the corresponding input
as the input clock source for
clock source for CMU1 PLL.
CMU1 PLL, this clock mux
clock
mux
clock
mux
CMU Channels
CMU0 PLL
CMU1 PLL
3.125 Gbps
1 Gbps
TX PLL
Logical
select
TX PLL
clock
Logical
mux
select
clock
mux
Full Duplex Transceiver Channel 1
Full Duplex Transceiver Channel 2
Stratix IV Device Handbook Volume 2: Transceivers
DIVIDER
TX CHANNEL 1
RX CHANNEL 1
LOCAL
3.125 Gbps
DIVIDER
RX CHANNEL 2
RX CDR
TX CHANNEL 2
LOCAL
RX CDR
1 Gbps
TX PMA + TX PCS
RX PMA + RX PCS
TX PMA + TX PCS
RX PMA + RX PCS
3.125 Gbps
3.125 Gbps
1 Gbps
1 Gbps
(1)
(1)
5–61