EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 141

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Figure 5–21. External Clock Outputs for Left and Right PLLs
Notes to
(1) You can feed these clock output pins using any one of the C[6..0], m counters.
(2) The CLKOUT0p and CLKOUT0n pins are dual-purpose I/O pins that you can use as two single-ended outputs or one single-ended output and
(3) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
February 2011 Altera Corporation
one external feedback input pin.
Figure
5–21:
f
PLL_<L2, L3, R2, R3>_CLKOUT0n/FB_CLKOUT0p (1), (2)
Any of the output counters (C[9..0] on the top and bottom PLLs and C[6..0] on the
left and right PLLs) or the M counter can feed the dedicated external clock outputs, as
shown in
all output pins available from a given PLL.
Each left and right PLL supports two clock I/O pins, configured as either two
single-ended I/Os or one differential I/O pair. When using both pins as single-ended
I/Os, one of them can be the clock output while the other pin is the external feedback
input (FB) pin. Therefore, for single-ended I/O standards, the left and right PLLs only
support external feedback mode.
Each pin of a single-ended output pair can either be in-phase or 180° out-of-phase.
The Quartus II software places the NOT gate in the design into the IOE to implement
the 180° phase with respect to the other pin in the pair. The clock output pin pairs
support the same I/O standards as standard output pins (in the top and bottom
banks) as well as LVDS, LVPECL, differential High-Speed Transceiver Logic (HSTL),
and differential SSTL.
To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the
Stratix IV PLLs can also drive out to any regular I/O pin through the GCLK or RCLK
network. You can also use the external clock output pins as user I/O pins if you do
not need external PLL clocking.
Figure 5–20
LEFT/RIGHT
PLLs
I/O Features in Stratix IV Devices
and
clkena0 (3)
m(fbout)
clkena1 (3)
PLL_<L2, L3, R2, R3>_FB_CLKOUT0p/CLKOUT0n (1), (2)
Figure
C0
C1
C2
C3
C4
C5
C6
5–21. Therefore, one counter or frequency can drive
chapter.
Internal Logic
Stratix IV Device Handbook Volume 1
5–25