EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 871

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Table 5–7. Channel Reconfiguration Classifications
February 2011 Altera Corporation
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By reconfiguring the CMU PLL connected to the
transceiver channel.
By selecting the alternate CMU PLL in the transceiver
block to supply clocks to the transceiver channel.
Every transmitter channel has one local clock divider.
Similarly, every receiver channel has one local clock
divider. You can reconfigure the data rate of a transceiver
channel by reconfiguring these local clock dividers to 1,
2, or 4. When you reconfigure these local clock dividers,
ensure that the functional mode of the transceiver
channel supports the reconfigured data rate.
1
1
1
1
Data Rate Reconfiguration
Channel and CMU PLL reconfiguration mode only affects the channel involved in the
reconfiguration (the transceiver channel specified by the logical_channel_address
port), without affecting the remaining transceiver channels controlled by the dynamic
reconfiguration controller.
You cannot reconfigure the auxiliary transmit (ATX) PLLs in Stratix IV transceivers.
Channel Reconfiguration Classifications
Table 5–7
In addition to the categories mentioned, you can also choose to reconfigure both the
data rate and functional mode of a transceiver channel.
For the following sections, assume that the transceiver channel has the Receiver and
Transmitter configuration in the ALTGX MegaWizard Plug-In Manager, unless
specified as Transmitter only or Receiver only.
The blocks that are reconfigured by this dynamic reconfiguration mode are the PCS
and PMA blocks of a transceiver channel, the local divider settings of the transmitter
and receiver channel, and the CMU PLL.
Blocks Reconfigured in Channel and CMU PLL Reconfiguration Mode
lists the classification for channel and CMU PLL reconfiguration mode.
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Use this feature to reconfigure the existing functional
mode of the transceiver channel to a totally different
functional mode.
There is no limit to the number of functional modes you
can reconfigure the transceiver channel to if the various
clocks involved support the transition. For more
information about core clocks, refer to
“Clocking/Interface Options” on page
Functional Mode Reconfiguration
Stratix IV Device Handbook Volume 2: Transceivers
5–30.
5–25