EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 799

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combination Requirements When You Enable Channel Reconfiguration
February 2011 Altera Corporation
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If you create an instance using the use additional CMU/ATX Transmitter PLLs from
outside the transceiver block option and place your transmitter channels in one
transceiver block (for example, QL1) and you use a CMU/ATX PLL from another
transceiver block (for example, QL0), the channels (if used) in QL0 must be connected
to the same reconfiguration controller as that of QL1.
using multiple PLLs.
Example 13
Consider that the following 12-channel design is targeted for a THREE transceiver
block per side device. The requirements for this design are:
1. Four transceiver channels to switch independently between four protocol data
2. Four transceiver channels to operate in SONET OC48 data rate.
3. Four transceiver channels to operate in GIGE data rate.
To implement step 1, you need four TX PLLs. Place the four channels in the middle
transceiver block (QL1—the left side was chosen for illustration purposes), and
provide one CMU PLL from QL0 for the SONET OC48 data rate and one CMU PLL
from QL2 for the GIGE data rate. Use the two CMU PLLs from QL1 for the FC 2G and
OTU1 data rates.
To implement step 2, note that the CMU PLL in QL0 already provides the SONET
OC48 data rate. Therefore, use the four channels in QL0 to run the SONET OC48 data
rate.
To implement step 3, note that the CMU PLL in QL2 already provides the GIGE data
rate. Therefore, use the four channels in QL2 to run the GIGE data rate.
Assign the same GXB TX PLL Reconfiguration group setting value for the
tx_dataout ports of all the instances. This is explained in
Requirements When You Enable the Use Alternate CMU PLL Option” on
page
Ensure that the requirements specified in
Channels” on page
PLLs” on page 3–10
rates (SONET OC48, FC 2G, GIGE, and OTU1).
3–42.
3–3,
are met.
“Sharing CMU PLLs” on page
“General Requirements to Combine
Stratix IV Device Handbook Volume 2: Transceivers
Example 13
3–5, and
“Combination
shows an instance
“Sharing ATX
3–45