EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 817

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
February 2011 Altera Corporation
As shown in
follow these reset steps:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
4. Wait for the rx_pll_locked signal from each channel to go high. The
5. In a bonded channel group, when the rx_pll_locked signal of all the channels
6. After asserting the rx_locktodata signal, wait for at least t
time between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted
during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
(marker 3), de-assert the tx_digitalreset signal (marker 4). For the receiver
operation, after de-assertion of the busy signal, wait for a minimum of two parallel
clock cycles to de-assert the rx_analogreset signal. After the rx_analogreset
signal is de-asserted, the receiver CDR of each channel starts locking to the
receiver input reference clock because rx_locktorefclk is asserted.
rx_pll_locked signal of each channel may go high at different times with respect
to each other (indicated by the slashed pattern at marker 7).
have gone high, from that point onwards, wait for at least t
de-assert rx_locktorefclk and assert rx_locktodata (marker 8). At this point, the
receiver CDR of all the channels enters into lock-to-data mode and starts locking to
the received data.
de-asserting rx_digitalreset (the time between markers 8 and 9).
Figure
4–5, for the receiver CDR in manual lock mode configuration,
Stratix IV Device Handbook Volume 2: Transceivers
LTD_Manual
LTR_LTD_Manual
pll_powerdown
before
, then
(the
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