EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 724

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–52
Table 2–14. FPGA Fabric-Transceiver Interface Clocks
Stratix IV Device Handbook Volume 2: Transceivers
reconfig_clk
cal_blk_clk
Notes to
(1) For more information about global, regional, and periphery clock resources available in each device, refer to the
(2) Ensure that the reconfig_clk is a free-running clock that is not derived from the transceiver blocks.
Clock Name
Stratix IV Devices
Table
FPGA Fabric-Transmitter Interface Clocking
(2)
2–11:
1
1
chapter.
Transceiver dynamic reconfiguration
clock
Transceiver calibration block clock
“FPGA Fabric-Transmitter Interface Clocking” on page 2–52
Fabric-Receiver Interface Clocking” on page 2–61
methodology to share transmitter and receiver phase compensation FIFO clocks in
order to reduce the global, regional, and periphery clock resource usage in your
design.
The transmitter phase compensation FIFO compensates for the phase difference
between the FPGA fabric clock (phase compensation FIFO write clock) and the
parallel transmitter PCS clock (phase compensation FIFO read clock). The transmitter
phase compensation FIFO write clock forms the FPGA fabric-Transmitter interface
clock. The phase compensation FIFO write clock and read clocks must have exactly
the same frequency (0 parts-per-million [PPM] frequency difference).
Stratix IV transceivers provide the following two options for selecting the transmitter
phase compensation FIFO write clock:
■
■
User-selection is provided to share transceiver datapath interface clocks in order to
reduce the global, regional, and periphery clock resource usage in your design.
Quartus II-Selected Transmitter Phase Compensation FIFO Write Clock
If you do not select the tx_coreclk port in the ALTGX MegaWizard
Manager, the Quartus II software automatically selects the transmitter phase
compensation FIFO write clock for each channel in that ALTGX instance. The
Quartus II software selects the FIFO write clock depending on the channel
configuration.
Non-Bonded Channel Configuration
In a non-bonded channel configuration, the transmitter channels may or may not be
identical. Identical transmitter channels are defined as channels that have exactly the
same CMU PLL input reference clock source, exactly the same CMU PLL
configuration, and exactly the same transmitter PMA and PCS configuration.
Identical transmitter channels may have different transmitter voltage output
differential ( V
“Quartus II-Selected Transmitter Phase Compensation FIFO Write Clock”
“User-Selected Transmitter Phase Compensation FIFO Write Clock” on page 2–58
Clock Description
OD
), transmitter common mode voltage (V
(Note 1)
FPGA fabric-to-transceiver
FPGA fabric-to-transceiver
(Part 2 of 2)
Interface Direction
Chapter 2: Transceiver Clocking in Stratix IV Devices
describe the criteria and
FPGA Fabric-Transceiver Interface Clocking
CM
), or pre-emphasis setting.
February 2011 Altera Corporation
and
Global clock
Global clock, Regional
clock
Resource Utilization
Clock Networks and PLLs in
“FPGA
FPGA Fabric Clock
™
Plug-In
(1)