EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 755

IC STRATIX IV FPGA 530K 1152HBGA

EP4SGX530HH35C2N

Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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SIV52003-4.1
Overview
Stratix IV Device Handbook Volume 2: Transceivers
February 2011
February 2011
SIV52003-4.1
f
This chapter describes the procedure for merging; for example, when combining
multiple protocols and data rates within a transceiver block. The instances you can
combine include Receiver Only and Transmitter and Receiver channels as well as
channels configured in Protocol Functional modes, channels using PLL cascade
clocks, channels in multiple transceiver blocks, and channels with a Basic (PMA
Direct) configuration. This chapter also offers several examples of sharing the clock
multiplier unit phase-locked loops (CMU PLLs).
For information about the supported data rate range for the auxiliary transmit
(ATX) PLL, refer to the “Transceiver Performance Specifications” section in the
and Switching Characteristics for Stratix IV Devices
Each transceiver channel in a Stratix
data rate or in an independent protocol mode. Within each transceiver channel, the
transmitter and receiver channels can run at different data rates. Each transceiver
block consists of two CMU PLLs that provide clocks to all the transmitter channels
within the transceiver block. Each receiver channel contains a dedicated clock data
recovery (CDR) unit.
In addition to the CMU PLLs, the ATX PLLs are available to provide clocks to the
transmitter channels that are configured for a specific data rate range.
This chapter includes the following sections:
“Glossary of Terms” on page 3–2
“Creating Transceiver Channel Instances” on page 3–3
“General Requirements to Combine Channels” on page 3–3
“Sharing CMU PLLs” on page 3–5
“Sharing ATX PLLs” on page 3–10
“Combining Receiver Only Channels” on page 3–10
“Combining Transmitter Channel and Receiver Channel Instances” on page 3–11
“Combining Transceiver Instances in Multiple Transceiver Blocks” on page 3–13
“Combining Transceiver Instances Using PLL Cascade Clocks” on page 3–16
“Combining Channels Configured in Protocol Functional Modes” on page 3–17
“Combining Transceiver Channels in Basic (PMA Direct) Configurations” on
page 3–25
“Combination Requirements When You Enable Channel Reconfiguration” on
page 3–42
3. Configuring Multiple Protocols and
Data Rates in Stratix IV Devices
®
IV GX and GT device can run at an independent
chapter.
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