EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 797
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combination Requirements When You Enable Channel Reconfiguration
February 2011 Altera Corporation
Example 12 shows the requirements.
Example 12
Consider that you intend to run four channels within the transceiver block to switch
between GIGE and SONET OC48 data rates. Assume that by default two channels run
at GIGE data rates and the other two channels run at SONET OC48 data rates.
Assume that Instance1 with two channels running at GIGE data rate is created with
the configuration, as listed in
Table 3–16. Combining Requirements with the Use Alternate CMU PLL Option Enabled—
Instance 1 for Example 12
Create Instance 2 with the following parameters to enable the Quartus II software to
share CMU PLLs between the two instances.
Table 3–17
Table 3–17. Combining Requirements with the Use Alternate CMU PLL Option Enabled—
Instance 2 for Example 12
Table 3–18
Instance 1 when you compile the design.
Table 3–18. Assignment for the GXB TX PLL Reconfiguration Group for Instance 1
To
Assignment Name
Value
Alternate PLL
Alternate PLL
Main PLL
Main PLL
Assignment
PLL
PLL
lists the required parameters to be set for Instance 2.
lists the assignment for the GXB TX PLL Reconfiguration group for
Data Rate (Gbps)
Data Rate (Gbps)
tx_dataout_instance1[0]
Note that the number of channels in this instance is 2. You can use any
one of the channel port names within this instance for this assignment.
GXB TX PLL Reconfiguration group setting
6
2.488
2.488
1.25
1.25
Table
3–16.
Input Reference Clock (MHz)
Input Reference Clock (MHz)
155.5
155.5
125
125
Stratix IV Device Handbook Volume 2: Transceivers
Setting
PLL Logical Reference
PLL Logical Reference
Index
Index
0
1
1
0
3–43
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