EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 297

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
February 2011 Altera Corporation
Receiver Hardware Blocks
The differential receiver has the following hardware blocks:
■
■
■
■
DPA Block
The DPA block takes in high-speed serial data from the differential input buffer and
selects one of the eight phases generated by the left and right PLL to sample the data.
The DPA chooses a phase closest to the phase of the serial data. The maximum phase
offset between the received data and the selected phase is 1/8 UI, which is the
maximum quantization error of the DPA. The eight phases of the clock are equally
divided, offering a 45
Figure 8–14
incoming serial data.
Figure 8–14. DPA Clock Phase to Serial Data Timing Relationship
Note to
(1) T
The DPA block continuously monitors the phase of the incoming serial data and
selects a new clock phase if needed. You can prevent the DPA from selecting a new
clock phase by asserting the optional RX_DPLL_HOLD port, which is available for each
channel.
“DPA Block” on page 8–19
“Synchronizer” on page 8–20
“Data Realignment Block (Bit Slip)” on page 8–20
“Deserializer” on page 8–22
VCO
Figure
is defined as the PLL serial clock period.
rx_in
8–14:
135˚
180˚
225˚
270˚
315˚
shows the possible phase relationships between the DPA clocks and the
45˚
90˚
0˚
0.125T
°
D0
resolution.
vco
D1
T
D2
vco
D3
D4
Stratix IV Device Handbook Volume 1
(Note 1)
Dn
8–19