EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 507

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
The following functional modes support the 10-bit PMA-PCS interface:
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This section describes the following word aligner 10-bit PMA-PCS interface modes:
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Table 1–27
10-bit PMA-PCS interface.
Table 1–27. Word Aligner Configurations with a 10-Bit PMA-PCS Interface
Protocols such as PCIe, XAUI, Gigabit Ethernet, and Serial RapidIO require the
receiver PCS logic to implement a synchronization state machine to provide hysteresis
during link synchronization. Each of these protocols defines a specific number of
synchronization code groups that the link must receive to acquire synchronization
and a specific number of erroneous code groups that it must receive to fall out of
synchronization.
In PCIe, XAUI, Gigabit Ethernet, and Serial RapidIO functional modes, the Quartus II
software configures the word aligner in automatic synchronization state machine
mode. It automatically selects the word alignment pattern length and pattern as
specified by each protocol. In each of these functional modes, the protocol-compliant
synchronization state machine is implemented in the word aligner.
PCIe
Serial RapidIO
XAUI
GIGE
SDI
Basic single-width
mode
PCIe Gen1 and Gen2
Serial RapidIO
XAUI
GIGE
SDI
Basic single-width mode
Automatic synchronization state machine mode with 10-bit PMA-PCS interface
mode
Manual alignment mode with 10-bit PMA-PCS interface mode
Bit-slip mode with 10-bit PMA-PCS interface mode
Functional Mode
Word Aligner in Single-Width Mode with 10-Bit PMA-PCS Interface Modes
Automatic Synchronization State Machine Mode Word Aligner with 10-Bit PMA-PCS
Interface Mode
lists the word aligner configurations allowed in functional modes with a
Automatic synchronization state machine
Automatic synchronization state machine
Automatic synchronization state machine
Automatic synchronization state machine
Bit-slip
Manual alignment, Automatic
synchronization state machine, Bit-slip
Allowed Word Aligner Configurations
Stratix IV Device Handbook Volume 2: Transceivers
Allowed Word Alignment
Pattern Length
7 bits, 10 bits
7 bits, 10 bits
7 bits, 10 bits
10 bits
10 bits
N/A
1–63