EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 828

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–22
Figure 4–12. Reset Sequence of PCIe Functional Mode
Notes to
(1) For t
(2) The minimum T1 and T2 period is 4 μs.
(3) The minimum T3 period is two parallel clock cycles.
Stratix IV Device Handbook Volume 2: Transceivers
Reset / Power Down Signals
Figure
pll_powerdown
PCIe Functional Mode
Output Status Signals
4–12:
duration, refer to the
pll _ powerdown
rx _ analogreset
rx _ pll _locked
rx _ freqlocked
tx _ digitalreset
rx _ digitalreset
pll _locked
You can configure PCIe functional mode with or without the receiver clock rate
compensation FIFO in the Stratix IV device. The reset sequence remains the same
whether or not you use the receiver clock rate compensation FIFO.
PCIe Reset Sequence
The PCIe protocol consists of an initialization/compliance phase and a normal
operation phase. The reset sequences for these two phases are described based on the
timing diagram in
busy
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
Initialization / Compliance Phase
2
Figure
Two parallel clock cycles
4–12.
3
4
5
6
7
8
9
Chapter 4: Reset Control and Power Down in Stratix IV Devices
T1 (2)
chapter.
10
Normal Operation Phase
Ignore receive data
11
February 2011 Altera Corporation
T2 (2)
Transceiver Reset Sequences
12
T3 (3)
13