EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 560

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–116
Figure 1–97. Transceiver Configurations in Basic Single-Width Mode with a 10-Bit PMA-PCS Interface for Stratix IV GT
Devices
Note to
(1) The maximum data rate specification shown in
Stratix IV Device Handbook Volume 2: Transceivers
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
(1)
(1)
TX PCS Latency
Interface Frequency
RX PCS Latency
Interface Frequency
Interface Frequency
other speed grades offered, refer to the
Data Rate (Gbps)
Low-Latency PCS
Channel Bonding
Rate Match FIFO
Encoder/Decoder
(Pattern Length)
Interface Width
FPGA Fabric-
FPGA Fabric-
Interface Width
FPGA Fabric-
Byte Ordering
Transceiver
Transceiver
FPGA Fabric
Word Aligner
Byte SerDes
Transceiver
Figure
Data Rate
PMA-PCS/Fabric
PMA-PCS
Interface Width
(MHz)
Functional
8B/10B
Modes
1–97:
9 - 11
Disabled
Disabled
0.6 - 2.5
8-bit
248 .8 -
5 - 6
10-bit
250
Disabled
Disabled
Single
Width
Manual Alignment
0.6 - 3.75
Disabled
4 - 5.5
Enabled
6 - 8
10-bit
124.4 –
20-bit
187.5
(7-bit, 10-bit)
Basic
16-bit
9 - 11
Disabled
Disabled
0.6 - 2.5
248 .8 -
5 - 6
8-bit
250
Double
Disabled
Width
Enabled
DC and Switching Characteristics
20-bit
0.6 - 3.75
Disabled
Enabled
4 - 5.5
124 .4 –
Stratix IV GT Configurations
6 - 8
16-bit
187.5
Figure 1–97
8
Disabled
Disabled
9 - 11
0.6 - 2.5
248.8 -
5 - 6
10-bit
250
Disabled
Disabled
0.6 - 3.75
Disabled
Enabled
4 - 5.5
124.4 –
6 - 8
20-bit
187.5
(7-bit, 10-bit)
Disabled
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
Bit-Slip
Disabled
0.6 - 2.5
Disabled
9 - 11
248.8 -
5 - 6
8-bit
250
Disabled
Enabled
PIPE
10-bit
0.6 - 3.75
Enabled
Disabled
124.4 –
6 - 8
4 - 5
16-bit
187.5
chapter.
XAUI
10-bit
9 - 11
Disabled
Disabled
0.6 - 2.5
248.8 -
5 - 6
10-bit
600 Mbps - 3.75 Gbps
250
Protocol
Disabled
Disabled
Basic Single Width
SRIO
10-bit
10-bit PMA-PCS
Interface Width
Chapter 1: Transceiver Architecture in Stratix IV Devices
x1, x4, x8
Enabled
0.6 - 3.75
Disabled
124 .4 –
4 - 5.5
6 - 8
20-bit
187.5
SONET
Synchronization
/SDH
8-bit
State Machine
(7-bit, 10-bit)
Automatic
Disabled
0.6 - 2.5
9 - 11
Disabled
248.8 -
5 - 6
8-bit
250
16-bit
(OIF)
CEI
Disabled
Disabled
16-bit
4 - 5.5
124.4 –
6 - 8
187 .5
10-bit
SDI
0.6 - 3.75
Enabled
Enabled
February 2011 Altera Corporation
4 - 5.5
6 - 8
124.4 –
10-Bit
Enabled
16-bit
187.5
Deterministic
Latency
Transceiver Block Architecture
Disabled
Disabled
20-Bit
0.6 - 2.5
248.8 -
5 - 6
20 -
8-bit
24
250
Enabled
0.6 - 3.75
Disabled
11.5 -
Enabled
14.5
124.4 –
4 - 5.5
16-bit
187 .5
Disabled
0.6 - 2.5
Disabled
3 - 4
10-bit
248.8 -
4 - 5
250
Disabled
Disabled
Disabled
Enabled
4 - 5
4 - 5
4 - 5
0.6 - 3.75
3 - 4. 5
Enabled
Disabled
4 - 5.5
124.4 –
20-bit
187.5
4 - 5.5
4 - 5.5
4 - 5.5