EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 535

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–78. 8B/10B Decoder in Control Code Group Detection
Figure 1–79. 8B/10 Decoder in 20-Bit Double-Width Mode
February 2011 Altera Corporation
CTRL[1..0]
MSB
19
j
1
1
h
18
1
rx_dataout[7..0]
15
H
The left side of
mode. In this mode, two 8B/10B decoders are cascaded for decoding the 20-bit
encoded data, as shown in
encoded data is decoded first and the ending running disparity is forwarded to the
8B/10B decoder responsible for decoding the 10-bit MSByte. The cascaded 8B/10B
decoder decodes the 20-bit encoded data into 16-bit data + 2-bit control identifier. The
MSB and LSB of the 2-bit control identifier corresponds to the MSByte and LSByte of
the 16-bit decoded data code group. The decoded data is fed to the byte deserializer or
the receiver phase compensation FIFO (if byte deserializer is disabled).
Each of the two cascaded 8B/10B decoders is compliant to Clause 36 in the IEEE802.3
specification.
The 8B/10B decoder operates in double-width mode only in Basic double-width
functional mode. You can enable or disable the 8B/10B decoder depending on your
proprietary protocol implementation.
Figure 1–79
identifier by the 8B/10B decoder in double-width mode.
1
rx_ctrldetect
g
17
datain[9..0 ]
1
G
14
8B/10B Decoder in Double-Width Mode
1
16
f
clock
1
13
F
1
15
i
1
13
E
shows a 20-bit code group decoded into 16-bit data and 2-bit control
1
D3.4
14
e
1
Figure 1–76 on page 1–89
11
D
1
13
d
1
10
C
D24.3
Cascaded 8B/10B Conversion
1
83
c
12
1
B
9
1
11
b
D28.5
Figure
1
78
A
8
1
10
a
1
H
7
K28.5
1–79. The 10-bit LSByte of the received 20-bit
BC
9
j
G
6
h
8
5
F
shows the 8B/10B decoder in double-width
BC
g
7
E
4
6
D
3
D15.0
f
0F
Stratix IV Device Handbook Volume 2: Transceivers
5
2
C
i
D0.0
00
1
B
e
4
0
A
d
3
D31.5
BF
Parallel Data
c
2
b
1
LSB
a
0
1–91