EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 886

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Table 5–10. rx_dataoutfull[63:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 1 of 6)
Stratix IV Device Handbook Volume 2: Transceivers
8-bit FPGA fabric-transceiver
Channel Interface
10-bit FPGA fabric-transceiver
Channel Interface
Channel Interface Description
FPGA Fabric-Transceiver
Table 5–10
signals.
lists the tx_dataoutfull[63:0] FPGA fabric-transceiver channel interface
The following signals are used in 8-bit 8B/10B modes:
rx_dataoutfull[7:0]: 8-bit decoded data (rx_dataout)
rx_dataoutfull[8]: Control bit (rx_ctrldetect)
rx_dataoutfull[9]: Code violation status signal (rx_errdetect)
rx_dataoutfull[10]: rx_syncstatus
rx_dataoutfull[11]: Disparity error status signal (rx_disperr)
rx_dataoutfull[12]: Pattern detect status signal (rx_patterndetect)
rx_dataoutfull[13]: Rate Match FIFO deletion status indicator
(rx_rmfifodatadeleted) in non-PCIe/PCIe modes.
rx_dataoutfull[14]: Rate Match FIFO insertion status indicator
(rx_rmfifodatainserted) in non-PCIe/PCIe modes.
rx_dataoutfull[14:13]: non-PCIe/PCIe mode (rx_pipestatus)
rx_dataoutfull[15]: 8B/10B running disparity indicator (rx_runningdisp)
The following signals are used in 8-bit SONET/SDH mode:
rx_dataoutfull[7:0]: 8-bit un-encoded data (rx_dataout)
rx_dataoutfull[8]: rx_a1a2sizeout
rx_dataoutfull[10]: rx_syncstatus
rx_dataoutfull[11]: Reserved
rx_dataoutfull[12]: rx_patterndetect
rx_dataoutfull[9:0]: 10-bit un-encoded data (rx_dataout)
rx_dataoutfull[10]: rx_syncstatus
rx_dataoutfull[11]: 8B/10B disparity error indicator (rx_disperr)
rx_dataoutfull[12]: rx_patterndetect
rx_dataoutfull[13]: Rate Match FIFO deletion status indicator
(rx_rmfifodatadeleted) in non-PCIe/PCIe modes
rx_dataoutfull[14]: Rate Match FIFO insertion status indicator
(rx_rmfifodatainserted) in non-PCIe/PCIe modes
rx_dataoutfull[15]: 8B/10B running disparity indicator (rx_runningdisp)
Receive Signal Description (Based on Stratix IV GX Supported FPGA
Fabric-Transceiver Channel Interface Widths)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation