EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 517
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
By default, the Stratix IV GX and GT receiver assumes a LSB-to-MSB transmission. If
the transmission order is MSB-to-LSB, the receiver forwards the bit-flipped version of
the parallel data to the FPGA fabric on the rx_dataout port. The receiver bit reversal
feature is available to correct this situation.
The receiver bit reversal feature is available through the rx_revbitordwa port only in
Basic single-width and double-width modes with the word aligner configured in
bit-slip mode. When the rx_revbitordwa signal is driven high in Basic single-width
mode, the 8-bit or 10-bit data D[7:0] or D[9:0] at the output of the word aligner gets
rewired to D[0:7] or D[0:9], respectively. When the rx_revbitordwa signal is driven
high in Basic double-width mode, the 16-bit or 20-bit data D[15:0] or D[19:0] at the
output of the word aligner gets rewired to D[0:15] or D[0:19], respectively.
Flipping the parallel data using this feature allows the receiver to forward the correct
bit-ordered data to the FPGA fabric on the rx_dataout port in the case of MSB-to-LSB
transmission.
Figure 1–55
datapath configurations.
Figure 1–55. Receiver Bit Reversal in Single-Width Mode
Receiver Bit Reversal
shows the receiver bit reversal feature in Basic single-width 10-bit wide
Output of Word Aligner before
RX bit reversal
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
rx_revbitordwa = high
Output of Word Aligner after RX
Stratix IV Device Handbook Volume 2: Transceivers
bit reversal
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
1–73
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