EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 943

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Examples
February 2011 Altera Corporation
Different Dynamic Reconfiguration Modes Involved
1. Channel and CMU PLL reconfiguration mode:
2. Channel and CMU PLL select reconfiguration mode:
3. The rx_tx_duplex_sel[1:0] port allows you to reconfigure the transmitter and
4. PMA controls reconfiguration mode used to configure the PMA settings for all the
For more information, refer to
on page
.mif Generation
The following .mifs are required for this example:
■
■
For more information, refer to
Various Dynamic Reconfiguration Transactions
The following dynamic reconfiguration transactions are required
page
■
■
■
1
■
1
receiver channels to operate at the different data rates.
channels.
For the seven regular transceiver channels, you must generate two .mifs. Use one
to move from a data rate of 2.5 Gbps to 5 Gbps and the other to revert back to
2.5 Gbps.
For the for PMA-only channels, you must generate two .mifs. Use one to move
from a data rate of 3.125 Gbps to 5 Gbps and the other to revert back to 3.125 Gbps.
.mif write transaction—for more information, refer to
Reconfiguration Mode Details” on page 5–24
Transmitter PLL Select Mode Details” on page
Reconfiguring PMA controls—for more information, refer to
Reconfiguring PMA Controls” on page
5–94:
is used for reconfiguring the seven regular transceiver channels from one data
rate to another using the same CMU0 PLL (in GXBR2)
is used for reconfiguring the four PMA-only channels from one data rate to
another using the CMU0 PLL (in GXBR0) and CMU1 PLL (GXBR0)
5–19.
This mode is chosen because both the receiver and transmitter of the
regular channels must be re-configured using a single CMU.
This mode is chosen because both the receiver and transmitter of the
regular channels must be re-configured and more than one CMU can be
used.
“Transceiver Channel Reconfiguration Mode Details”
“Memory Initialization File (.mif)” on page
5–13.
and
Stratix IV Device Handbook Volume 2: Transceivers
5–47.
“Channel Reconfiguration with
“Channel and CMU PLL
“Dynamically
“Example 1” on
5–20.
5–97